With regards to wireless receiver systems, the effects of NOISE from all the folLOWing phases can be reduced using the gain of the LOW-NOISE AMPLIFIER ((LNA)). Therefore, boosting the specified signal power without adding a lot of NOISE and distortion will be necessary for the signal to be retrievable in the later phases or stages of the system. The proposed method in this study for NOISE reduction is based on the combination of two techniques: reversed-phase NOISE signal and non-reversed phase signal. The theoretical model for NOISE cancellation is presented along with the equations for the overall NOISE value, which are derived based on a two-port model. The circuit design is implemented using the 𝑇 𝑆 𝑀 𝐶 0. 18 𝜇 𝑚 𝐶 𝑀 𝑂 𝑆 𝑅 𝐹 technology on a Cadence Spectre RF tool. The current study also implemented a CMOS UWB (LNA) configuration with inter-stage matching as well as shunt-series inductive peaking. This design uses inductive source degeneration cascode technology along with an inter-stage matching network. Moreover, to boost impedance matching and power gain, a Chebyshev band pass filter is placed at the input while a shunt-series inductive peaking is placed at the output.

This paper examines the effects of operating point and device size on the high frequency NOISE parameters in CMOS technology, to eliminate high power dissipation challenge in simultaneous NOISE and input matching (SNIM) technique. Modified technique is applied to improve power dissipation problem, NOISE performance, gain and input/output matching of the (LNA) at center frequency of 5.2 GHz. The (LNA) is implemented in TSMC 0.18-µm CMOS process. Post-layout simulation results demonstrate (LNA) has reached to power consumption of 2.1 mW under 1.4 V supply while having, 2.71 dB NOISE figure, 1GHz Band-width, 16.38 dB power gain, -40.42 dB reverse isolation factor, -21.5 dB and -23.59 dB input/output return loss respectively.

The most important challenges in ultra wideband LOW NOISE AMPLIFIERs ((LNA)s) are flatness of gain, input impedance matching and LOWer NOISE figure at desired frequencies. In this paper, an ultra wideband LOW NOISE AMPLIFIER with flat gain and LOW NOISE figure at frequencies between 3. 1GHz to 10. 6 GHz is proposed. In the proposed circuit, a cascade stage is used as a main block and NOISE cancellation method is used for increasing gain and LOWering NOISE figure. To have good input and output matching, active feedback is used. In addition feedback and RLC load is used for better flatness for gain of (LNA). The proposed circuit is designed and simulated in TSMC 90nm CMOS Technology using HSpice simulator. Simulations show NOISE figure of 1. 62-2. 1dB, flat gain in the range of 11. 9-12dB and power consumption of 11. 72mW in the frequency range of 3. 1-10. 6GHz.

The LOW NOISE AMPLIFIER ((LNA)) stands as a crucial element RF receiver chain, demanding a delicate interplay of characteristics such as high gain, LOW NOISE figure (NF), superior linearity, and an extensive dynamic range. De-signing an ultrawideband (UWB) (LNA) poses a complex challenge as engineers grapple with intricate trade-offs inherent in these parameters. To address these challenges, NOISE cancellation techniques have emerged as valuable tools, revolutionizing the design of UWB (LNA)s by relaxing the traditional trade-off between bandwidth and input matching. This innovative approach not only enhances bandwidth but also effectively cancels out the un-desirable NOISE and nonlinearities from the input MOSFET. Despite the advancements afforded by NOISE cancellation, the broad bandwidth of UWB (LNA)s presents a significant hurdle. If the linearity is insufficient, the UWB (LNA) faces performance degradation due to increase in-band interference. In response, this article proposes an inventive linearization technique, a combination of NOISE Cancelling (NC) and complementary derivative super-position (CDS), aiming to increase the linearity of UWB (LNA)s. Through meticulous simulations conducted using Cadence Virtuoso with GPDK090 library, the proposed (LNA) showcases impressive performance metrics across the UWB spectrum. Notably, it achieves a gain ranging from 12.5 dB to 15.5 dB, a NOISE figure within the range of 3.9 dB to 5.26 dB, and an IIP3 spanning from 6.3 dBm to 8.8 dBm. Remarkably, this innovative (LNA) accomplishes these feats while operating with a modest power consumption of 11.36 mW from a 1.2 V supply. This groundbreaking technique holds promise for significantly enhancing the efficiency and overall performance of UWB (LNA)s within contemporary RF receiver systems.

In this paper, a new method for extending and relaxing the NOISE-coupling (NC) technique is proposed to enhance the NOISE-shaping order without adding the number of integrators. The NOISE-shaping order of the introduced ∑∆ modulator whit applying a second-order NOISE-coupling technique is enhanced and its performance with optimizing the NOISE transfer function (NTF) zeros is improved. Also, by removing the analog adder at feedforward path and transferring it to a new feedback branch before the last integrator and adding second-order NC path can be decreased the input voltage swing to the quantizer. Thus, by improving the modulator resolution, power consumption can be reduced. Mathematical analyses and behavioural simulation results confirm the effectiveness of the new NC method. To examine its performance, a 2nd-order single loop ΣΔ modulator was designed. The new NOISE-coupling method is used to achieve the three-order NOISE shaping to increase the resolution with LOW complexity and LOW-power. The results show an outstanding improvement in signal-to-NOISE and distortion ratio (SNDR) compared to the conventional structure.

High gain Balun-LOW-NOISE-AMPLIFIER ((LNA)) is proposed for tuner of digital televisions (DTVs). The proposed Balun-(LNA) is based on CS-CG (common-source-common-gate) structure. To improve the isolasion and frequency response, Balun-(LNA) has cascode transistors before load resistors. Balun-(LNA) uses current-bleeding circuit to increasie transconductance of CS transistor, so that current-bleeding transistor has transconductance of N-1 times larger than transconductance of cascode transistor. Thereby, transconductance and current of CS transistor are increased N times, as N-1 times of current pass to current-bleeding transistor. Therefore current of CG and CS stages stay identical. Also, Balun-(LNA) employs a positive feedback to satisfy input impedance matching and CG transistor has higher transconductance. By increasing transconductance of CS and CG transistors, the proposed Balun-(LNA) achieves to high voltage gain. Accordingly, CG and CS tansistors have symmetrical currents and loads at the differential output of the proposed Balun-(LNA). Symmetrical loads cause the balanced differential outputs. This proposed Balun-(LNA) is designed in 90-nm CMOS technology and covers the frequency range of 40 MHz to 1GHz. This Balun-(LNA) achieves the voltage gain of 22.6 dB, S11 of less than -10 dB and the Minimum NF of 5 dB. This Balun-(LNA) operates at the nominal supply voltage of 2.2v.

In this paper, a LOW NOISE Variable Gain AMPLIFIER in Ka-frequency band is designed. This AMPLIFIER is digitally controlled by using switching transistors which change the gain with an accuracy of 5-bit resolution (32 steps). The output phase shift should be minimized within a Dynamic Range of 15 dB. The proposed structure includes a LOW NOISE AMPLIFIER and a Variable Gain AMPLIFIER, with common-source structure and degenerative inductor. In the proposed structure, the main gain is achieved by (LNA) and the switching control bits are used in two stages of the VGA. Simulation illustrates a NOISE Figure of 5. 6 dB; bandwidth of 5. 34 GHz; S11, S22 less than-14 dB and Dynamic Range of 15 dB. By using a “ compensating inductor” in the source of switching transistors, the amount of phase shift was reduced, such that within the bandwidth of 1. 5 GHz it is less than 5 degrees. The post-layout simulation results, show a Dynamic Range of 18. 7 dB; a bandwidth of 2. 5 GHz; NOISE Figure of 6. 4 dB and return losses less than-10 dB. In addition to it, In EM analysis, all inductors and major RF paths are evaluated by “ Sonnet” software.

In this paper, a new design of concurrent dual-band LOW NOISE AMPLIFIER ((LNA)) for multi-band single-channel Global Navigation Satellite System (GNSS) receivers is proposed. This new structure is able to operate concurrently at frequency of 1.2 and 1.57 GHz. Parallel and series resonance parts are employed in the input matching in order to achieve concurrent performance. With respect to used pseudo-differential structure, (LNA) is basically a single-ended-to-differential conversion and it consequently has no need to balun. In addition, an inductively degenerated cascode approach is employed to have better simultaneous matching and NOISE Figure (NF). Simulations are performed with TSMC 0.18μm technology in ADS software. Results analysis present that (LNA) achieves input matchings of -11.024 and -13.131 dB, NFs of 2.315 and 2.333 dB, gains of 26.926 and 27.576 dB, P-1dB of -15.3 and -13 dBm, IIP3 of -0.9 and 2.2 dBm at 1.2 and 1.57 GHz, respectively. Besides, (LNA) consumes 8.32 mA DC current from a 1.8 V supply voltage.

Along with increasing in the number of telecommunication standards, the demand for multi-standard transmitters / receivers has been raised. The aim of this paper is to design and simulate an (LNA) that covers the full band of UWB and involve the available standards as well. Accordingly, the main design parameters including NOISE, gain, input matching, current level, and voltage level are determined so as to achieve an effective operation in the band of 3. 1 GHz to 10. 6 GHz. The proposed structure is a differential common-gate associated with the gain-boosting and current-reused techniques. Applying the proposed common-gate structure in the (LNA) in CMOS 0. 18μ m technology, the power consumption achieves a considerable reduction compared to other (LNA) counterparts. In addition, the NOISE figure is reduced to 1. 8dB with a gain of 12. 8 dB to 13. 6 dB, a linearity of-7dBm is achieved, and the input reflection coefficient is reduced to less than-10 dB.